Abstract : The increasing real-time processing requirements have lead to the significant use of heterogeneous computing architectures. In this context, the time-critical tasks are frequently processed by a coarsely configurable pipelined FPGA-based hardware. Obviously, the manual application mapping on this architectures leads to a tedious work. In this paper, we resume the first results of our approach to the automated mapping of a real-life application on a data stream pipeline-based architecture.
https://hal-enpc.archives-ouvertes.fr/hal-01801018 Contributeur : Eva DokladalovaConnectez-vous pour contacter le contributeur Soumis le : lundi 28 mai 2018 - 10:09:11 Dernière modification le : samedi 15 janvier 2022 - 03:56:30 Archivage à long terme le : : mercredi 29 août 2018 - 12:40:37
Elias Barbudo, Eva Dokladalova, Thierry Grandpierre, Laurent George. A mapping tool for configurable pipeline co-processors. Colloque National du GDR SoC-SiP, GDR-SOC-SIP, Jun 2018, Paris, France. ⟨hal-01801018⟩