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Communication Dans Un Congrès Année : 2018

A mapping tool for configurable pipeline co-processors


The increasing real-time processing requirements have lead to the significant use of heterogeneous computing architectures. In this context, the time-critical tasks are frequently processed by a coarsely configurable pipelined FPGA-based hardware. Obviously, the manual application mapping on this architectures leads to a tedious work. In this paper, we resume the first results of our approach to the automated mapping of a real-life application on a data stream pipeline-based architecture.
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hal-01801018 , version 1 (28-05-2018)


  • HAL Id : hal-01801018 , version 1


Elias Barbudo, Eva Dokladalova, Thierry Grandpierre, Laurent George. A mapping tool for configurable pipeline co-processors. Colloque National du GDR SoC-SiP, GDR-SOC-SIP, Jun 2018, Paris, France. ⟨hal-01801018⟩
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