A mapping tool for configurable pipeline co-processors

Elias Barbudo (1, 2) , Eva Dokladalova (1, 2) , Thierry Grandpierre (2) , Laurent George (2)

1 ESIEE Paris
2 LIGM - Laboratoire d'Informatique Gaspard-Monge

The increasing real-time processing requirements have lead to the significant use of heterogeneous computing architectures. In this context, the time-critical tasks are frequently processed by a coarsely configurable pipelined FPGA-based hardware. Obviously, the manual application mapping on this architectures leads to a tedious work. In this paper, we resume the first results of our approach to the automated mapping of a real-life application on a data stream pipeline-based architecture.

Domaines: Architectures Matérielles [cs.AR]; Traitement des images [eess.IV]; Traitement du signal et de l'image [eess.SP]

Elias Barbudo, Eva Dokladalova, Thierry Grandpierre, Laurent George. A mapping tool for configurable pipeline co-processors. Colloque National du GDR SoC-SiP, GDR-SOC-SIP, Jun 2018, Paris, France. ⟨hal-01801018⟩